Invention Grant
US07986040B2 Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
有权
在半导体器件中通孔图案化期间减少金属覆盖层侵蚀的方法
- Patent Title: Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
- Patent Title (中): 在半导体器件中通孔图案化期间减少金属覆盖层侵蚀的方法
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Application No.: US12397661Application Date: 2009-03-04
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Publication No.: US07986040B2Publication Date: 2011-07-26
- Inventor: Christin Bartsch , Daniel Fischer , Matthias Schaller
- Applicant: Christin Bartsch , Daniel Fischer , Matthias Schaller
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson
- Priority: DE102008021568 20080430
- Main IPC: H01L23/522
- IPC: H01L23/522

Abstract:
During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
Public/Granted literature
- US20090273086A1 METHOD OF REDUCING EROSION OF A METAL CAP LAYER DURING VIA PATTERNING IN SEMICONDUCTOR DEVICES Public/Granted day:2009-11-05
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