Invention Grant
US07994059B2 Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
有权
通过在半导体器件中的双应力衬垫上方使用附加应力层来增强层间电介质中的应力转移
- Patent Title: Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
- Patent Title (中): 通过在半导体器件中的双应力衬垫上方使用附加应力层来增强层间电介质中的应力转移
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Application No.: US11865796Application Date: 2007-10-02
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Publication No.: US07994059B2Publication Date: 2011-08-09
- Inventor: Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
- Applicant: Ralf Richter , Martin Gerhardt , Martin Mazur , Joerg Hohage
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102007004824 20070131; DE102007016897 20070410
- Main IPC: H01L21/331
- IPC: H01L21/331
Abstract:
By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
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