Invention Grant
US08014485B2 Techniques for integrated circuit clock management using multiple clock generators
有权
使用多个时钟发生器的集成电路时钟管理技术
- Patent Title: Techniques for integrated circuit clock management using multiple clock generators
- Patent Title (中): 使用多个时钟发生器的集成电路时钟管理技术
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Application No.: US11750290Application Date: 2007-05-17
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Publication No.: US08014485B2Publication Date: 2011-09-06
- Inventor: Bill K. C. Kwan , Craig Eaton , Daniel W. Bailey
- Applicant: Bill K. C. Kwan , Craig Eaton , Daniel W. Bailey
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Main IPC: H03D3/24
- IPC: H03D3/24
Abstract:
A clock generator system (400) includes a phase locked loop (PLL) (402), a first clock generator (404), and a second clock generator (406). The PLL (402) includes a first output configured to provide a first clock signal at a first frequency and a second output configured to provide a second clock signal at the first frequency. The second clock signal is out-of-phase with the first clock signal. An output of the first clock generator (404) is configured to provide a first generated clock signal whose effective frequency is based on both the first and second clock signals and a first mode signal. An output of the second clock generator (406) is configured to provide a second generated clock signal whose effective frequency is based on both the first and second clock signals and a second mode signal.
Public/Granted literature
- US20080285696A1 Techniques for integrated circuit clock management using multiple clock generators Public/Granted day:2008-11-20
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