Invention Grant
US08050042B2 Clock routing in multiple channel modules and bus systems and method for routing the same
失效
多通道模块和总线系统中的时钟路由及其路由方法
- Patent Title: Clock routing in multiple channel modules and bus systems and method for routing the same
- Patent Title (中): 多通道模块和总线系统中的时钟路由及其路由方法
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Application No.: US11190561Application Date: 2005-07-26
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Publication No.: US08050042B2Publication Date: 2011-11-01
- Inventor: Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
- Applicant: Ravindranath T. Kollipara , David Nguyen , Belgacem Haba
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: H05K7/02
- IPC: H05K7/02 ; H05K7/06 ; H05K7/08 ; H05K7/10

Abstract:
The terminating module and method include integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.
Public/Granted literature
- US20050254221A1 Clock routing in multiple channel modules and bus systems Public/Granted day:2005-11-17
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