公开(公告)号：US09442540B2

公开(公告)日：2016-09-13

申请号：US12634441

申请日：2009-12-09

Applicant: Tung M. Nguyen ,  Richard Au ,  David Nguyen ,  Tipatat Chennavasin ,  Najaf Rizvi ,  David Bradley ,  Matthew Humphreys

Inventor： Tung M. Nguyen ,  Richard Au ,  David Nguyen ,  Tipatat Chennavasin ,  Najaf Rizvi ,  David Bradley ,  Matthew Humphreys

IPC: G06F13/00 ,  H05K7/10 ,  G06F1/20 ,  H05K5/00 ,  H05K7/20 ,  G06F1/26 ,  G06F1/18

CPC classification number: G06F9/44505 ,  G06F1/181 ,  G06F1/189 ,  G06F1/20 ,  G06F1/26 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

Abstract: A multi-node computer system, comprising: a plurality of nodes, a system control unit and a carrier board. Each node of the plurality of nodes comprises a processor and a memory. The system control unit is responsible for: power management, cooling, workload provisioning, native storage servicing, and I/O. The carrier board comprises a system fabric and a plurality of electrical connections. The electrical connections provide the plurality of nodes with power, management controls, system connectivity between the system control unit and the plurality of nodes, and an external network connection to a user infrastructure. The system control unit and the carrier board provide integrated, shared resources for the plurality of nodes. The multi-node computer system is provided in a single enclosure.

Abstract translation: 一种多节点计算机系统，包括：多个节点，系统控制单元和载板。 多个节点中的每个节点包括处理器和存储器。 系统控制单元负责：电源管理，冷却，工作负载配置，本机存储服务和I / O。 承载板包括系统结构和多个电连接。 电连接为多个节点提供功率，管理控制，系统控制单元和多个节点之间的系统连接以及到用户基础设施的外部网络连接。 系统控制单元和载板为多个节点提供集成的共享资源。 多节点计算机系统提供在单个机箱中。

公开(公告)号：US20130138721A1

公开(公告)日：2013-05-30

申请号：US13307451

申请日：2011-11-30

Applicant: Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

Inventor： Paul O'Connell ,  David Nguyen ,  George White ,  Matt Crist ,  Michael Tuccinard ,  Matthew Stuehler ,  Michael Novak

IPC: G06F15/16

CPC classification number: G06Q40/06

Abstract: A finds comparison tool is provided that includes a presentation tier providing a plurality of interfaces for interacting with a plurality of client applications. The presentation tier allows the client applications to send requests for a plurality of analytics to be performed regarding comparing the performance of one or more funds or portfolios as well allowing mobile-based client applications and web-based client applications to communicate with the funds comparison tool. An application tier processes the requests sent by the client applications by providing the data used by the client applications, storing and retrieving of session data, and an interface for the analytics information captured during sessions so as to allow a visualization of the analytics used in the comparison of the one or more funds or portfolios.

Abstract translation: 提供了一种查找比较工具，其包括提供用于与多个客户端应用程序交互的多个界面的表示层。 表示层允许客户端应用程序发送关于比较一个或多个资金或组合的性能的多个分析请求，并允许基于移动的客户端应用程序和基于Web的客户端应用程序与资金比较工具进行通信 。 应用程序层通过提供客户端应用程序使用的数据，存储和检索会话数据以及用于在会话期间捕获的分析信息的界面来处理客户端应用程序发送的请求，以便允许可视化在 比较一个或多个基金或投资组合。

公开(公告)号：US08302041B1

公开(公告)日：2012-10-30

申请号：US12146313

申请日：2008-06-25

Applicant: Vi Chi Chan ,  Tetse Jang ,  Kevin Chung ,  Taneem Ahmed ,  David Nguyen Van Mau ,  Mehrdad Parsa ,  Amit Singh

Inventor： Vi Chi Chan ,  Tetse Jang ,  Kevin Chung ,  Taneem Ahmed ,  David Nguyen Van Mau ,  Mehrdad Parsa ,  Amit Singh

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5054

Abstract: A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.

Abstract translation: 实现包括可编程逻辑器件内的初始网络的电路设计的计算机实现的方法可以包括根据第一合成技术从电路设计产生第一选择网络并确定第一选择网络的布局。 根据第二合成技术，可以从第一选择网络生成至少第二选择网络。 可以确定用于第二选择网络的位置。 可以将第一选择网络的位置与第二选择网络的位置进行比较。 可以根据比较选择一个布局和相应的选择网络，并输出。

公开(公告)号：US08297987B2

公开(公告)日：2012-10-30

申请号：US13211100

申请日：2011-08-16

Applicant: David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

Inventor： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC: H05K5/03

CPC classification number: G06K19/07732

Abstract: An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

Abstract translation: 本文描述了扩展通用串行总线（USB）存储设备。 根据一个实施例，扩展的USB存储设备包括具有闪存设备和安装在其上的闪存控制器的印刷电路板组件（PCBA），以及耦合到PCBA的扩展USB连接器插头，用于在外部 设备和闪存设备和闪存控制器，其中扩展的USB连接器插头包括用于耦合到外部设备的第一端和耦合到闪存设备和闪存控制器的第二端。 扩展的USB连接器插头包括多个通信接口。 还描述了其它方法和装置。

公开(公告)号：US20120005437A1

公开(公告)日：2012-01-05

申请号：US13230741

申请日：2011-09-12

Applicant: Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

Inventor： Richard M. Barth ,  Frederick A. Ware ,  Donald C. Stark ,  Craig E. Hampel ,  Paul G. Davis ,  Abhijit M. Abhyankar ,  James A. Gasbarro ,  David Nguyen

IPC: G06F12/00

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

Abstract: A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Abstract translation: 存储器控制器具有在第一组互连资源上传送指定激活一行存储器单元的第一命令的接口，指定针对存储器单元行的写操作的第二命令，指定 是否与写入操作相关地进行预充电，指定是否将与写入操作相关联地发布数据掩码信息的代码，以及如果代码指定将发出数据掩码信息的数据掩码信息，指定是否选择性地 写入与写入操作相关联的写入数据的部分。 存储器控制器接口还通过第二组互连资源与第一组互连资源（写入数据）分离。

公开(公告)号：US20120001670A1

公开(公告)日：2012-01-05

申请号：US13235251

申请日：2011-09-16

Applicant: Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

Inventor： Ravindranath T. Kollipara ,  David Nguyen ,  Belgacem Haba

IPC: G06F1/04

CPC classification number: G11C5/04 ,  G06F13/409 ,  G11C5/00 ,  H05K1/023 ,  H05K1/117 ,  H05K1/141 ,  H05K1/147 ,  H05K1/148 ,  H05K7/1459 ,  H05K2201/10189

Abstract: The terminating module includes integrated circuits and a termination circuit which receive clock signals from the integrated circuit. The integrated circuit includes at least one memory integrated circuit mounted on a printed circuit board. An electrical connector is configured to couple the terminating module to a motherboard. Additionally, the termination circuit includes a resistor. In another embodiment, the terminating module provides a printed circuit board, a memory integrated circuit mounted on the circuit board, a terminator circuit which includes a resistor, and an electrical connector. The electrical connector couples the terminating module to a motherboard.

Abstract translation: 终端模块包括集成电路和从集成电路接收时钟信号的终端电路。 集成电路包括安装在印刷电路板上的至少一个存储器集成电路。 电连接器被配置为将终端模块耦合到主板。 另外，终端电路包括电阻器。 在另一个实施例中，端接模块提供印刷电路板，安装在电路板上的存储器集成电路，包括电阻器和电连接器的终端电路。 电连接器将终端模块耦合到主板。

公开(公告)号：US20110300724A1

公开(公告)日：2011-12-08

申请号：US13211100

申请日：2011-08-16

Applicant: David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

Inventor： David Nguyen ,  Nan Nan ,  Jim Chin-Nan Ni ,  Frank I-Kang Yu ,  Abraham C. Ma ,  Ming-Shiang Shen

IPC: H05K5/03

CPC classification number: G06K19/07732

Abstract: An extended universal serial bus (USB) storage device is described herein. According to one embodiment, an extended USB storage device includes a printed circuit board assembly (PCBA) having a flash memory device and a flash controller mounted thereon, and an extended USB connector plug coupled to the PCBA for providing a USB compatible interface between an external device and the flash memory device and the flash controller, wherein the extended USB connector plug includes a first end used to couple to the external device and a second end coupled to the flash memory device and the flash controller. The extended USB connector plug includes multiple communication interfaces. Other methods and apparatuses are also described.

Abstract translation: 本文描述了扩展通用串行总线（USB）存储设备。 根据一个实施例，扩展的USB存储设备包括具有闪存设备和安装在其上的闪存控制器的印刷电路板组件（PCBA），以及耦合到PCBA的扩展USB连接器插头，用于在外部 设备和闪存设备和闪存控制器，其中扩展的USB连接器插头包括用于耦合到外部设备的第一端和耦合到闪存设备和闪存控制器的第二端。 扩展的USB连接器插头包括多个通信接口。 还描述了其它方法和装置。

公开(公告)号：US20110229583A1

公开(公告)日：2011-09-22

申请号：US12726326

申请日：2010-03-17

Applicant: David Van Tran ,  David Nguyen Tran

Inventor： David Van Tran ,  David Nguyen Tran

IPC: A61K33/40 ,  A61P31/04 ,  A61P29/00 ,  A61P31/10 ,  A61P33/00 ,  A61P19/02 ,  A61P31/12 ,  A61P17/00

CPC classification number: A61K33/40 ,  A61K31/185

Abstract: A medicinal drug is administered to a person for treating a medical condition of the person or/and for preventing the person from contracting the medical condition. The medical condition can be a bacterial infection, a eukaryotic infection, a prion-caused infection, a non-pathogenic inflammation, and, insofar as not covered by any of these four types of the medical condition, a fungal infection, a spore-caused infection, and a parasitic infection. A medicinal drug is similarly administered non-topically to a person for treating a virus-caused medical condition of the person or/and for preventing the person from contracting the virus-caused medical condition. The medicinal drug is typically formed at least partially with salt of peroxymonosulfuric acid, preferably potassium hydrogen peroxymonosulfate.

Abstract translation: 药物被用于治疗患者的医疗状况或/或用于防止该人感染医疗状况的人。 医疗状况可以是细菌感染，真核感染，朊病毒引起的感染，非致病性炎症，并且在这四种类型的医学病症中没有被覆盖，真菌感染，孢子引起的 感染和寄生虫感染。 类似地，药物非局部地用于治疗患者的病毒引起的医疗状况或/或用于防止该人感染病毒引起的疾病的人。 药物通常至少部分地与过氧单硫酸盐，优选过硫酸氢钾一起形成。

公开(公告)号：US08015348B2

公开(公告)日：2011-09-06

申请号：US12980591

申请日：2010-12-29

Applicant: Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

Inventor： Charles C. Lee ,  I-Kang Yu ,  David Nguyen ,  Abraham Chih-Kang Ma ,  Ming-Shiang Shen

IPC: G06F12/08

CPC classification number: H05K1/182 ,  G06F12/00 ,  H01R13/447 ,  H05K1/181 ,  H05K5/0278 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1572

Abstract: Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.

Abstract translation: 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

公开(公告)号：US07735045B1

公开(公告)日：2010-06-08

申请号：US12047184

申请日：2008-03-12

Applicant: David Nguyen Van Mau ,  Yassine Rjimati

Inventor： David Nguyen Van Mau ,  Yassine Rjimati

IPC: G06F17/50

CPC classification number: G06F17/5054

Abstract: Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design is identified. The chain of flip-flops includes first and second control signals. A shift register is instantiated in a logical description of the circuit design for the chain of flip-flops. A shift register is instantiated in the logical description for the chain of flip-flops. First and second control chains of flip-flops are instantiated in the logical description for the first and second control signals, respectively. A multiplexer is instantiated in the logical description and is configured to select among an output of the shift register, an asserted logic state, and a de-asserted logic state based on outputs of the first and second control chains.

Abstract translation: 描述了将触发器逻辑映射到移位寄存器逻辑上的方法和装置。 在一个示例中，提供了在集成电路中实现的电路设计中处理触发器逻辑的方法。 确定了电路设计中的触发器链。 触发器链包括第一和第二控制信号。 在触发器链的电路设计的逻辑描述中实例化移位寄存器。 在触发器链的逻辑描述中实例化移位寄存器。 触发器的第一和第二控制链分别在第一和第二控制信号的逻辑描述中被实例化。 多路复用器在逻辑描述中被实例化，并且被配置为基于第一和第二控制链的输出在移位寄存器的输出，被断言的逻辑状态和取消置位的逻辑状态之间进行选择。