Invention Grant
- Patent Title: Phase-locked loop integrated circuits having dual feedback control
- Patent Title (中): 具有双重反馈控制的锁相环集成电路
-
Application No.: US12571868Application Date: 2009-10-01
-
Publication No.: US08054115B2Publication Date: 2011-11-08
- Inventor: Jong-shin Shin
- Applicant: Jong-shin Shin
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2008-0098160 20081007
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump.
Public/Granted literature
- US20100085092A1 Phase-Locked Loop Integrated Circuits Having Dual Feedback Control Public/Granted day:2010-04-08
Information query