公开(公告)号：US08624625B2

公开(公告)日：2014-01-07

申请号：US13440457

申请日：2012-04-05

Applicant: Jong-Shin Shin ,  Chi-Won Kim

Inventor： Jong-Shin Shin ,  Chi-Won Kim

IPC: H03K17/16 ,  H04B3/00

CPC classification number: H03K19/017545 ,  H03K19/00315

Abstract: A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

Abstract translation: 用于HDMI发送器的终端电路包括在正传输引脚和负传输引脚之间并联连接的偏置单元和终端电阻器单元。 偏置单元通过选择通过正传输引脚接收的第一电压和通过负传输引脚接收的第二电压之间的较高电压来产生偏置电压。 终端电阻单元形成在由偏置电压偏置的阱区上，并且响应于终端电阻器控制信号有条件地在正传输引脚和负传输引脚之间提供终端电阻。 终端电路有条件地提供终端电阻而没有漏电流。 终端电阻可以通过使用n位控制代码来改变。

公开(公告)号：US08243867B2

公开(公告)日：2012-08-14

申请号：US12314211

申请日：2008-12-05

Applicant: Jong-Shin Shin

Inventor： Jong-Shin Shin

IPC: H04L7/00

CPC classification number: H04L7/02 ,  H03L7/00 ,  H04L7/0012 ,  H04L7/005

Abstract: A receiver may include a clock and data recovery circuit, a detection circuit and a sampling clock generator. The clock and data recovery circuit may receive first data and sample the first data to generate recovered data in response to a reception sampling clock signal. The detection circuit may detect a frequency difference between a transmission sampling clock signal and the reception sampling clock signal by comparing the first data and the reception sampling clock signal to generate a frequency difference detection signal. The sampling clock generator may generate the reception sampling clock signal based on the frequency difference detection signal and a first reference clock signal. Therefore, a communication system including the receiver may effectively reduce a jitter noise.

Abstract translation: 接收机可以包括时钟和数据恢复电路，检测电路和采样时钟发生器。 时钟和数据恢复电路可以接收第一数据并且对第一数据进行采样以响应于接收采样时钟信号产生恢复的数据。 检测电路可以通过比较第一数据和接收采样时钟信号来检测发送采样时钟信号和接收采样时钟信号之间的频率差，以产生频差检测信号。 采样时钟发生器可以基于频差检测信号和第一参考时钟信号产生接收采样时钟信号。 因此，包括接收机的通信系统可以有效地减少抖动噪声。

公开(公告)号：US20100090771A1

公开(公告)日：2010-04-15

申请号：US12570144

申请日：2009-09-30

Applicant: Jong-shin Shin

Inventor： Jong-shin Shin

IPC: H03K3/00

CPC classification number: H03K3/0315

Abstract: A digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

Abstract translation: 数字控制振荡器包括环形振荡器，连接到环形振荡器的第一端子并且具有根据数字代码变化的电阻的并联电阻器组和连接到环形振荡器的第二端子的串联电阻器组，并且具有 电阻根据数字代码而变化。 环形振荡器的频率随并联电阻组的电阻的变化和串联电阻组的电阻根据数字代码而线性变化。

公开(公告)号：US20080074154A1

公开(公告)日：2008-03-27

申请号：US11833362

申请日：2007-08-03

Applicant: Jong-Shin Shin

Inventor： Jong-Shin Shin

IPC: H03B21/00

CPC classification number: H03B21/00

Abstract: A spread-spectrum clock generator includes: a phase interpolator mixing a plurality of clock signals, which differ from each other in phase, and modulating a clock signal resulting from mixing the clock signals; and a controller generating a control signal to generate weights of the plurality of clock signals for modulating the clock signal. The phase interpolator regulates a modulation speed of the clock by adjusting a generation speed of the weights.

Abstract translation: 扩频时钟发生器包括：相位插值器，其混合彼此相位不同的多个时钟信号，并调制由混合时钟信号产生的时钟信号; 以及产生控制信号以产生用于调制时钟信号的多个时钟信号的权重的控制器。 相位内插器通过调整权重的生成速度来调节时钟的调制速度。

公开(公告)号：US20070036253A1

公开(公告)日：2007-02-15

申请号：US11496692

申请日：2006-07-31

Applicant: Il-Won Seo ,  Jong-Shin Shin

Inventor： Il-Won Seo ,  Jong-Shin Shin

IPC: H04L7/00

CPC classification number: H03L7/093

Abstract: For updating a gain of a loop filter from a timing error signal, a timing signal estimator generates a current timing signal estimation value from a prior timing error estimation value, a prior gain value, and a prior timing signal estimation value. A timing error estimator generates a current timing error estimation value from a timing error accumulation value and the current timing signal estimation value. A current gain value of the loop filter is determined from the current timing error estimation value.

Abstract translation: 为了从定时误差信号更新环路滤波器的增益，定时信号估计器从先前的定时误差估计值，先前的增益值和先前的定时信号估计值产生当前定时信号估计值。 定时误差估计器根据定时误差累积值和当前定时信号估计值产生当前定时误差估计值。 根据当前定时误差估计值确定环路滤波器的当前增益值。

公开(公告)号：US20060170459A1

公开(公告)日：2006-08-03

申请号：US11340458

申请日：2006-01-27

Applicant: Jong-Shin Shin ,  Ji-Young Kim ,  Myoung-Bo Kwak ,  Il-Won Seo ,  Chi-Won Kim ,  Hyun-Goo Kim ,  Jae-Hyun Park

Inventor： Jong-Shin Shin ,  Ji-Young Kim ,  Myoung-Bo Kwak ,  Il-Won Seo ,  Chi-Won Kim ,  Hyun-Goo Kim ,  Jae-Hyun Park

IPC: H03K19/094

CPC classification number: H03K17/693

Abstract: A multiplexer and methods thereof. In an example, the multiplexer may receive a first periodic signal with a first active duration and a second periodic signal with a second active duration, the first and second active durations not overlapping. The multiplexer may transition statuses of first and second transmission gates based on the first and second periodic signals, respectively, such that each of the first and second transmission gates are set to the same status during at least one time period (e.g., between the first and second active durations where both the first and second periodic signals are inactive). In a further example, the example multiplexer may include first and second transmission gates receiving first and second input signals which may be controlled by the first and second control signals.

Abstract translation: 多路复用器及其方法。 在一个示例中，多路复用器可以接收具有第一有效持续时间的第一周期性信号和具有第二有效持续时间的第二周期信号，第一和第二有效持续时间不重叠。 复用器可以分别基于第一和第二周期信号转换第一和第二传输门的状态，使得第一和第二传输门中的每一个在至少一个时间段内（例如，在第一和第二周期信号之间）被设置为相同的状态 和第二有效持续时间，其中第一和第二周期信号都不起作用）。 在另一示例中，示例多路复用器可以包括接收可由第一和第二控制信号控制的第一和第二输入信号的第一和第二传输门。

公开(公告)号：US20060098714A1

公开(公告)日：2006-05-11

申请号：US11205014

申请日：2005-08-17

Applicant: Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

Inventor： Jong-shin Shin ,  Duck-hyun Chang ,  Ji-young Kim ,  Myoung-bo Kwak ,  Il-won Seo ,  Jae-Hyun Park ,  Hyun-goo Kim ,  Chi-won Kim

IPC: H04B1/69

CPC classification number: H03L7/18 ,  H03B23/00 ,  H03L7/0891

Abstract: A spread spectrum clock generator (SSCG) and method of generating a spread spectrum clock (SSC) signal, in which the SSCG may include a controller outputting a given modulation voltage signal based on a difference between an average frequency of a first feedback signal and a comparison frequency signal input thereto, or based on comparison in total phase variations between a second feedback signal and the comparison frequency signal, and a sub-system for generating a first control voltage as a function of an input reference frequency signal and a second feedback signal input thereto. An adder may add the first control voltage signal and the modulation voltage signal to generate a second control voltage signal, and a voltage control oscillator (VCO) may generate the SSC signal based on the second control voltage signal.

公开(公告)号：US09094023B2

公开(公告)日：2015-07-28

申请号：US13228520

申请日：2011-09-09

Applicant: Jong Shin Shin

Inventor： Jong Shin Shin

IPC: H03D3/24 ,  H03L7/081 ,  H03L7/18 ,  H03L7/099 ,  H03L7/197 ,  H04L27/00

CPC classification number: H03L7/081 ,  H03L7/0996 ,  H03L7/18 ,  H03L7/1974 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0069

Abstract: A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.

Abstract translation: 提供了一个分数N锁相环。 分数N锁相环包括相位调整电路，其检测参考时钟信号和反馈时钟信号之间的相位差，并响应于检测到的相位差输出多个相位时钟信号，相位选择器选择并输出 响应于相位选择信号从相位调整电路输出的多个相位时钟信号，控制电路，通过使用Σ-Δ调制器操作时钟信号产生相位选择信号，该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以 每个N个或更多个不同的整数（N是大于或等于2的整数），以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。

公开(公告)号：US08229053B2

公开(公告)日：2012-07-24

申请号：US11833362

申请日：2007-08-03

Applicant: Jong-Shin Shin

Inventor： Jong-Shin Shin

IPC: H03D3/24 ,  H04B1/69

CPC classification number: H03B21/00

Abstract: A spread-spectrum clock generator includes: a phase interpolator mixing a plurality of clock signals, which differ from each other in phase, and modulating a clock signal resulting from mixing the clock signals; and a controller generating a control signal to generate weights of the plurality of clock signals for modulating the clock signal. The phase interpolator regulates a modulation speed of the clock by adjusting a generation speed of the weights.

Abstract translation: 扩频时钟发生器包括：相位插值器，其混合彼此相位不同的多个时钟信号，并调制由混合时钟信号产生的时钟信号; 以及产生控制信号以产生用于调制时钟信号的多个时钟信号的权重的控制器。 相位内插器通过调整权重的生成速度来调节时钟的调制速度。

公开(公告)号：US20120063521A1

公开(公告)日：2012-03-15

申请号：US13228520

申请日：2011-09-09

Applicant: Jong Shin Shin

Inventor： Jong Shin Shin

IPC: H03D3/24 ,  H03L7/08 ,  H04L27/00

CPC classification number: H03L7/081 ,  H03L7/0996 ,  H03L7/18 ,  H03L7/1974 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0069

Abstract: A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.

Abstract translation: 提供了一个分数N锁相环。 分数N锁相环包括相位调整电路，其检测参考时钟信号和反馈时钟信号之间的相位差，并响应于检测到的相位差输出多个相位时钟信号，相位选择器选择并输出 响应于相位选择信号从相位调整电路输出的多个相位时钟信号，控制电路，通过使用Σ-Δ调制器操作时钟信号产生相位选择信号，该Σ-Δ调制器操作时钟信号是通过将选择的相位时钟信号除以 每个N个或更多个不同的整数（N是大于或等于2的整数），以及通过将所选择的相位时钟信号除以整数来产生反馈时钟信号的第一分频器。