Invention Grant
- Patent Title: Materials, structures and methods for microelectronic packaging
- Patent Title (中): 微电子封装的材料,结构和方法
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Application No.: US11986998Application Date: 2007-11-27
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Publication No.: US08129823B2Publication Date: 2012-03-06
- Inventor: Ravindra V. Tanikella
- Applicant: Ravindra V. Tanikella
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L23/52

Abstract:
Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.
Public/Granted literature
- US20080087986A1 Materials, structures and methods for microelectronic packaging Public/Granted day:2008-04-17
Information query
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