Invention Grant
US08183106B2 Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio
有权
用于制造具有掩埋扩散电介质结构和增加的栅极耦合比的浮动栅极存储器件的装置和相关方法
- Patent Title: Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio
- Patent Title (中): 用于制造具有掩埋扩散电介质结构和增加的栅极耦合比的浮动栅极存储器件的装置和相关方法
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Application No.: US11460216Application Date: 2006-07-26
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Publication No.: US08183106B2Publication Date: 2012-05-22
- Inventor: Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
- Applicant: Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
- Applicant Address: TW
- Assignee: Macronix International Co., Ltd.
- Current Assignee: Macronix International Co., Ltd.
- Current Assignee Address: TW
- Agency: Baker & McKenzie LLP
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/336 ; H01L21/8238
Abstract:
A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
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