公开(公告)号：US07888272B2

公开(公告)日：2011-02-15

申请号：US11609747

申请日：2006-12-12

Applicant: Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

Inventor： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC: H01L21/318

CPC classification number: H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

Abstract translation: 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

公开(公告)号：US20100085809A1

公开(公告)日：2010-04-08

申请号：US12636095

申请日：2009-12-11

Applicant: Yung-Feng LIN ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

Inventor： Yung-Feng LIN ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5642 ,  G11C2211/5634

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract translation: 一种多位闪存及其读取方法。 提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。 在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。 然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

公开(公告)号：US07710774B2

公开(公告)日：2010-05-04

申请号：US11285919

申请日：2005-11-23

Applicant: Yin Jen Chen ,  Chun Lein Su ,  Ming Shiang Chin ,  Chih Chieh Yeh ,  Tzung Ting Han

Inventor： Yin Jen Chen ,  Chun Lein Su ,  Ming Shiang Chin ,  Chih Chieh Yeh ,  Tzung Ting Han

IPC: G11C16/04 ,  G11C5/06

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11568

Abstract: A NAND type multi-bit charge storage memory array comprises a first and a second memory strings each of which includes one or more charge storage memory cells and two select transistors. The charge storage memory cells are connected in series to form a memory cell string. The two select transistors are connected in series to both ends of the memory cell string, respectively. The NAND type multi-bit charge storage memory array further comprises a shared bit line and a first and a second bit lines. The shared bit line is connected with the first ends of the first and the second memory strings. The first and the second bit lines are connected to the second ends of the first and the second memory strings, respectively. The first select transistor and the second select transistor of each memory string are controlled by a first and a second select transistor control lines, respectively.

Abstract translation: NAND型多位电荷存储存储器阵列包括第一和第二存储器串，每个存储器串包括一个或多个电荷存储存储单元和两个选择晶体管。 电荷存储存储单元串联连接以形成存储单元串。 两个选择晶体管分别串联连接到存储单元串的两端。 NAND型多位电荷存储存储器阵列还包括共享位线和第一位线和第二位线。 共享位线与第一和第二存储器串的第一端连接。 第一和第二位线分别连接到第一和第二存储器串的第二端。 每个存储器串的第一选择晶体管和第二选择晶体管分别由第一和第二选择晶体管控制线控制。

公开(公告)号：US07643337B2

公开(公告)日：2010-01-05

申请号：US11826574

申请日：2007-07-17

Applicant: Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

Inventor： Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

IPC: G11C7/00

CPC classification number: G11C11/5642 ,  G11C2211/5634

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract translation: 一种多位闪存及其读取方法。 提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。 在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。 然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

公开(公告)号：US20080138998A1

公开(公告)日：2008-06-12

申请号：US11609747

申请日：2006-12-12

Applicant: Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

Inventor： Kuan Fu Chen ,  Yin Jen Chen ,  Tzung Ting Han ,  Ming-Shang Chen ,  Shih Chin Lee

IPC: H01L21/31

CPC classification number: H01L21/3144 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/42332 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/7885

Abstract: A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.

Abstract translation: 半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。 然而，额外的步骤不需要额外的掩模。 因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

公开(公告)号：US20080026527A1

公开(公告)日：2008-01-31

申请号：US11460216

申请日：2006-07-26

Applicant: Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

Inventor： Kuan Fu Chen ,  Yin Jen Chen ,  Meng Hsuan Weng ,  Tzung Ting Han ,  Ming Shang Chen ,  Chun Pei Wu

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

Abstract: A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.

Abstract translation: 一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。 因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。 此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

公开(公告)号：US20070269947A1

公开(公告)日：2007-11-22

申请号：US11435459

申请日：2006-05-16

Applicant: Kuei-Yun Chen ,  Chun-Lien Su ,  Yin-Jen Chen ,  Ming-Shang Chen

Inventor： Kuei-Yun Chen ,  Chun-Lien Su ,  Yin-Jen Chen ,  Ming-Shang Chen

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method for manufacturing a NAND flash memory is provided. First, a substrate is provided. Next, a tunneling dielectric layer, a first conductive layer and a mask layer are sequentially formed on the substrate. Next, a plurality of isolation structures is formed in the mask layer, the first conductive layer, the tunneling dielectric layer and the substrate. Next, the mask layer is removed, so that the top surface of each isolation structure is higher than that of the first conductive layer. Next, a second conductive layer is formed on the exposed sidewalls of the isolation structures. Next, an inter-gate dielectric layer and a third conductive layer are sequentially formed on the substrate.

Abstract translation: 提供一种制造NAND闪速存储器的方法。 首先，提供基板。 接下来，在衬底上依次形成隧穿介质层，第一导电层和掩模层。 接下来，在掩模层，第一导电层，隧道电介质层和基板中形成多个隔离结构。 接下来，去除掩模层，使得每个隔离结构的顶表面高于第一导电层的顶表面。 接下来，在隔离结构的暴露的侧壁上形成第二导电层。 接下来，在衬底上依次形成栅极间电介质层和第三导电层。

公开(公告)号：US08552528B2

公开(公告)日：2013-10-08

申请号：US13240589

申请日：2011-09-22

Applicant: Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming Shang Chen

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming Shang Chen

IPC: H01L23/52 ,  H01L29/40 ,  G11C5/06 ,  G11C17/00

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

公开(公告)号：US08111547B2

公开(公告)日：2012-02-07

申请号：US12636095

申请日：2009-12-11

Applicant: Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

Inventor： Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

IPC: G11C11/34

CPC classification number: G11C11/5642 ,  G11C2211/5634

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract translation: 一种多位闪存及其读取方法。 提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。 在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。 然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

公开(公告)号：US20120008363A1

公开(公告)日：2012-01-12

申请号：US13240589

申请日：2011-09-22

Applicant: Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming Shang Chen

Inventor： Kuan-Fu Chen ,  Yin-Jen Chen ,  Tzung-Ting Han ,  Ming Shang Chen

IPC: G11C17/16 ,  G11C17/00

CPC classification number: G11C17/16 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/101

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract translation: 一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体 并且设置成与第一行导体相邻并且与第二行导体相邻。 阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。