Invention Grant
- Patent Title: Write combining cache with pipelined synchronization
- Patent Title (中): 将组合缓存与流水线同步相结合
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Application No.: US12128149Application Date: 2008-05-28
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Publication No.: US08190826B2Publication Date: 2012-05-29
- Inventor: Laurent Lefebvre , Michael Mantor , Robert Hankinson
- Applicant: Laurent Lefebvre , Michael Mantor , Robert Hankinson
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Sterne, Kessler, Goldstein & Fox P.L.L.C.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F13/00 ; G06F13/28

Abstract:
Systems and methods for pipelined synchronization in a write-combining cache are described herein. An embodiment to transmit data to a memory to enable pipelined synchronization of a cache includes obtaining a plurality of synchronization events for transactions with said memory, calculating one or more matches between said events and said data stored in one or more cache-lines of said cache, storing event time stamps of events associated with said matches, generating one or more priority values based on said event time stamps, concurrently transmitting said data to said memory based on said priority values.
Public/Granted literature
- US20090300288A1 Write Combining Cache with Pipelined Synchronization Public/Granted day:2009-12-03
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