Invention Grant
US08195583B2 Correlating instruction sequences with CPU performance events to improve software performance
有权
将指令序列与CPU性能事件相关联,以提高软件性能
- Patent Title: Correlating instruction sequences with CPU performance events to improve software performance
- Patent Title (中): 将指令序列与CPU性能事件相关联,以提高软件性能
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Application No.: US12472820Application Date: 2009-05-27
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Publication No.: US08195583B2Publication Date: 2012-06-05
- Inventor: Gary R. Frost
- Applicant: Gary R. Frost
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Hamilton & Terrile, LLP
- Agent Gary W. Hamilton
- Main IPC: G06F15/18
- IPC: G06F15/18

Abstract:
A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern.
Public/Granted literature
- US20100306514A1 Correlating Instruction Sequences with CPU Performance Events to Improve Software Performance Public/Granted day:2010-12-02
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