Invention Grant
US08195583B2 Correlating instruction sequences with CPU performance events to improve software performance 有权
将指令序列与CPU性能事件相关联,以提高软件性能

Correlating instruction sequences with CPU performance events to improve software performance
Abstract:
A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern.
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