Invention Grant
US08214575B2 Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices
有权
存储器模块具有配置用于在同步存储器件上顺序到达信号的信号线
- Patent Title: Memory module having signal lines configured for sequential arrival of signals at synchronous memory devices
- Patent Title (中): 存储器模块具有配置用于在同步存储器件上顺序到达信号的信号线
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Application No.: US12975313Application Date: 2010-12-21
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Publication No.: US08214575B2Publication Date: 2012-07-03
- Inventor: Haw-Jyh Liaw , David Nguyen
- Applicant: Haw-Jyh Liaw , David Nguyen
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Morgan, Lewis & Bockius LLP
- Main IPC: G06F13/42
- IPC: G06F13/42
Abstract:
A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.
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