Invention Grant
US08258041B2 Method of fabricating metal-bearing integrated circuit structures having low defect density
有权
制造具有低缺陷密度的金属轴承集成电路结构的方法
- Patent Title: Method of fabricating metal-bearing integrated circuit structures having low defect density
- Patent Title (中): 制造具有低缺陷密度的金属轴承集成电路结构的方法
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Application No.: US12816381Application Date: 2010-06-15
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Publication No.: US08258041B2Publication Date: 2012-09-04
- Inventor: Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
- Applicant: Srinivas Raghavan , Kalyan Cherukuri , Thomas E. Lillibridge , Richard A. Faust
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method of fabricating metal-bearing structures in an integrated circuit such as metal-polysilicon capacitors using conductive metal compounds. Defects due to organometallic polymers formed during the etch of a hard mask material are minimized by using a process that includes a plasma etch for the hard mask that achieves a predominantly chemical character using a fluorine-based etch chemistry. Using a low-temperature liquid-phase strip of the hard mask photoresist instead of an ash prevents further cross-linking of polymers formed during the plasma etch. Etching the metal-bearing material using a hot fully-concentrated mixture of ammonium hydroxide and hydrogen peroxide allows short etch times that are particularly shortened for tantalum nitride films deposited with a nitrogen concentration of about 30 percent or greater.
Public/Granted literature
- US20110306207A1 METHOD OF FABRICATING METAL-BEARING INTEGRATED CIRCUIT STRUCTURES HAVING LOW DEFECT DENSITY Public/Granted day:2011-12-15
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