Invention Grant
US08294273B2 Methods for fabricating and filling conductive vias and conductive vias so formed
有权
制造和填充如此形成的导电通孔和导电通孔的方法
- Patent Title: Methods for fabricating and filling conductive vias and conductive vias so formed
- Patent Title (中): 制造和填充如此形成的导电通孔和导电通孔的方法
-
Application No.: US12985570Application Date: 2011-01-06
-
Publication No.: US08294273B2Publication Date: 2012-10-23
- Inventor: Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
- Applicant: Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: TraskBritt
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
Public/Granted literature
- US20110095429A1 METHODS FOR FABRICATING AND FILLING CONDUCTIVE VIAS AND CONDUCTIVE VIAS SO FORMED Public/Granted day:2011-04-28
Information query
IPC分类: