A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.