Semiconductor device fabrication method including hard mask and sacrificial spacer elements

Invention Grant

US08372706B2 Semiconductor device fabrication method including hard mask and sacrificial spacer elements 有权

Title translation: 包括硬掩模和牺牲隔离元件的半导体器件制造方法

Please log in to see more content

Patent Title: Semiconductor device fabrication method including hard mask and sacrificial spacer elements
Patent Title (中): 包括硬掩模和牺牲隔离元件的半导体器件制造方法
Application No.: US13218720

Application Date: 2011-08-26
Publication No.: US08372706B2

Publication Date: 2013-02-12
Inventor: Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
Applicant: Shun-Jang Liao , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Haynes and Boone, LLP
Main IPC: H01L21/8238
IPC: H01L21/8238

Semiconductor device fabrication method including hard mask and sacrificial spacer elements

Abstract:

Provided is a method of fabricating a semiconductor device. A first hard mask layer is formed on a substrate. A second hard mask layer s formed the substrate overlying the first hard mask layer. A dummy gate structure on the substrate is formed on the substrate by using at least one of the first and the second hard mask layers to pattern the dummy gate structure. A spacer element is formed adjacent the dummy gate structure. A strained region on the substrate adjacent the spacer element (e.g., abutting the spacer element). The second hard mask layer and the spacer element are then removed after forming the strained region.

Abstract(Chinese):

提供一种制造半导体器件的方法。在基板上形成第一硬掩模层。第二硬掩模层形成覆盖在第一硬掩模层上的基板。通过使用第一和第二硬掩模层中的至少一个来在衬底上形成伪栅极结构，以对虚拟栅极结构进行图案化。在虚拟栅极结构附近形成间隔元件。邻近衬垫元件的衬底上的应变区域（例如，邻接间隔元件）。然后在形成应变区域之后去除第二硬掩模层和间隔元件。

Public/Granted literature

US20110312141A1 SEMICONDUCTOR DEVICE FABRICATION METHOD INCLUDING HARD MASK AND SACRIFICIAL SPACER ELEMENTS Public/Granted day:2011-12-22

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS