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    Hybrid shallow trench isolation for high-k metal gate device improvement
    2.
    发明授权
    Hybrid shallow trench isolation for high-k metal gate device improvement 有权
    混合浅沟槽隔离用于高k金属栅极器件的改进

    公开(公告)号：US08367515B2

    公开(公告)日：2013-02-05

    申请号：US12330347

    申请日：2008-12-08

    Applicant: Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

    Inventor： Chung Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

    IPC: H01L21/76

    CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/105

    Abstract: A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a substrate including a first region and a second region; forming at least one isolation region having a first aspect ratio in the first region and at least one isolation region having a second aspect ratio in the second region; performing a high aspect ratio deposition process to form a first layer over the first and second regions of the substrate; removing the first layer from the second region; and performing a high density plasma deposition process to form a second layer over the first and second regions of the substrate.

    Abstract translation: 公开了一种制造具有改进性能的半导体器件的方法。 该方法包括提供包括第一区域和第二区域的衬底; 在所述第一区域中形成具有第一纵横比的至少一个隔离区域和在所述第二区域中具有第二纵横比的至少一个隔离区域; 执行高纵横比沉积工艺以在所述基板的所述第一和第二区域上形成第一层; 从第二区域去除第一层; 以及执行高密度等离子体沉积工艺以在所述衬底的所述第一和第二区域上形成第二层。

    Poly resistor and poly eFuse design for replacement gate technology
    4.
    发明授权
    Poly resistor and poly eFuse design for replacement gate technology 有权
    Poly电阻和poly eFuse设计替代栅极技术

    公开(公告)号：US08324046B2

    公开(公告)日：2012-12-04

    申请号：US13174368

    申请日：2011-06-30

    Applicant: Kong-Beng Thei ,  Harry Chuang

    Inventor： Kong-Beng Thei ,  Harry Chuang

    IPC: H01L21/8234

    CPC classification number: H01L27/0629 ,  H01L23/5256 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: Methods for fabricating a semiconductor device are disclosed. In an example, a method includes forming an isolation region on a substrate, wherein the isolation region extends a depth into the substrate from a substrate surface; forming a recess in the isolation region, wherein the recess is defined by a concave surface of the isolation region; and forming a first gate structure over the substrate surface and a second gate structure over the concave surface of the isolation region.

    Abstract translation: 公开了制造半导体器件的方法。 在一个实例中，一种方法包括在衬底上形成隔离区域，其中隔离区域从衬底表面向衬底延伸深度; 在所述隔离区域中形成凹部，其中所述凹部由所述隔离区域的凹面限定; 以及在所述衬底表面上形成第一栅极结构，以及在所述隔离区域的所述凹表面上方形成第二栅极结构。

    Method of fabricating spacers in a strained semiconductor device
    6.
    发明授权
    Method of fabricating spacers in a strained semiconductor device 有权
    在应变半导体器件中制造间隔物的方法

    公开(公告)号：US08143131B2

    公开(公告)日：2012-03-27

    申请号：US12415021

    申请日：2009-03-31

    Applicant: Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

    Inventor： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

    Abstract translation: 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

    Low leakage capacitors including portions in inter-layer dielectrics
    8.
    发明授权
    Low leakage capacitors including portions in inter-layer dielectrics 有权
    低漏电容器，包括层间电介质中的部分

    公开(公告)号：US08120086B2

    公开(公告)日：2012-02-21

    申请号：US12331109

    申请日：2008-12-09

    Applicant: Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

    Inventor： Oscar M. K. Law ,  Kong-Beng Thei ,  Harry Chuang

    IPC: H01L27/108 ,  H01L29/94

    CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An integrated circuit structure includes a semiconductor substrate including a first region and a second region; an insulation region in the second region of the semiconductor substrate; and an inter-layer dielectric (ILD) over the insulation region. A transistor is in the first region. The transistor includes a gate dielectric and a gate electrode over the gate dielectric. A first conductive line and a second conductive line are over the insulation region. The first conductive line and the second conductive line are substantially parallel to each other and extending in a first direction. A first metal line and a second metal line are in a bottom metal layer (M1) and extending in the first direction. The first metal line and the second metal line substantially vertically overlap the first conductive line and the second conductive line, respectively. The first metal line and the second metal line form two capacitor electrodes of a capacitor.

    Abstract translation: 集成电路结构包括：包括第一区域和第二区域的半导体衬底; 半导体衬底的第二区域中的绝缘区域; 和绝缘区域上的层间电介质（ILD）。 晶体管处于第一区域。 晶体管包括栅极电介质和位于栅极电介质上的栅电极。 第一导线和第二导线在绝缘区上方。 第一导线和第二导线基本上彼此平行并沿第一方向延伸。 第一金属线和第二金属线位于底部金属层（M1）中并沿第一方向延伸。 第一金属线和第二金属线分别基本上垂直地与第一导线和第二导线重叠。 第一金属线和第二金属线形成电容器的两个电容器电极。

    Gate control and endcap improvement
    9.
    发明授权
    Gate control and endcap improvement 有权
    门控和端帽改进

    公开(公告)号：US08105929B2

    公开(公告)日：2012-01-31

    申请号：US12193538

    申请日：2008-08-18

    Applicant: Harry Chuang ,  Kong-Beng Thei

    Inventor： Harry Chuang ,  Kong-Beng Thei

    IPC: H01L21/38

    CPC classification number: H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/4966 ,  Y10S438/917

    Abstract: A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

    Abstract translation: 形成半导体结构的方法包括以下步骤。 在有源区中的衬底上形成栅介电层。 栅极电极层形成在栅极介电层上。 在栅电极层上形成第一光刻胶。 蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。 第一张光刻胶被去除。 形成覆盖栅极结构的第二光致抗蚀剂。 去除不受第二光致抗蚀剂保护的虚拟图案。 然后移除第二个光刻胶。

    Device scheme of HKMG gate-last process
    10.
    发明授权
    Device scheme of HKMG gate-last process 有权
    HKMG最终进程的设备方案

    公开(公告)号：US08058119B2

    公开(公告)日：2011-11-15

    申请号：US12536878

    申请日：2009-08-06

    Applicant: Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

    Inventor： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

    IPC: H01L21/8238

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

    Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

    Abstract translation: 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

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