Invention Grant
US08390634B2 Buffer management in vector graphics hardware 有权
矢量图形硬件中的缓冲区管理

Buffer management in vector graphics hardware
Abstract:
A graphics processor or a graphics block for use in a processor includes a type buffer used for determining if a currently processed pixel requires further processing. Each pixel has a number of sub-pixels and each sub-pixel line includes at least one counter that is stored in an edge buffer. A limited edge buffer that can store edge buffer values in a limited range can be employed. Each buffer can include information regarding the whole screen or a portion of thereof. The edge buffer also can be an external or internal buffer, and when implemented internally, the graphics processor or graphics block need not employ a bi-directional bus.
Public/Granted literature
Information query
Patent Agency Ranking
0/0