Invention Grant
US08493173B2 Method of cavity forming on a buried resistor layer using a fusion bonding process
失效
使用熔接工艺在掩埋电阻层上形成腔体的方法
- Patent Title: Method of cavity forming on a buried resistor layer using a fusion bonding process
- Patent Title (中): 使用熔接工艺在掩埋电阻层上形成腔体的方法
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Application No.: US13082444Application Date: 2011-04-08
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Publication No.: US08493173B2Publication Date: 2013-07-23
- Inventor: Ashwinkumar C. Bhatt , Norman A. Card , Charles Buchter
- Applicant: Ashwinkumar C. Bhatt , Norman A. Card , Charles Buchter
- Applicant Address: US NY Endicott
- Assignee: Endicott Interconnect Technologies, Inc.
- Current Assignee: Endicott Interconnect Technologies, Inc.
- Current Assignee Address: US NY Endicott
- Agency: Hinman, Howard & Katell, LLP
- Agent Mark Levy
- Main IPC: H01C1/02
- IPC: H01C1/02

Abstract:
A method of forming a buried resistor within a cavity for use in electronic packages using two glass impregnated dielectric layers, one with a clearance hole, the second with a resistor core, the clearance hole being placed over the resistor core and the assembly fusion bonded. The space remaining around the resistor core is filled with a soldermask material and the assembly is coated with metal. Thru-holes are drilled, cleaned, and plated and then the metal coating is etched and partially removed. The soldermask is then removed and a layer of gold plating is applied to the exposed metal surfaces. The use of glass impregnated dielectric layers and fusion bonding eliminates the fluorinated ethylene propylene resin (FEP) bleed problem associated with previous buried resistor cavity assemblies.
Public/Granted literature
- US20120256722A1 METHOD OF CAVITY FORMING ON A BURIED RESISTOR LAYER USING A FUSION BONDING PROCESS Public/Granted day:2012-10-11
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