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US08497723B2 Low-hysteresis high-speed differential sampler 有权
低滞后高速差分采样器

Low-hysteresis high-speed differential sampler
Abstract:
A low-hysteresis high-speed latch circuit is disclosed which isolates a sample stage and hold stage from one another during a latch clock phase and simultaneously shorts the output nodes together during the latch clock phase to reduce hysteresis of the latch.
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