Invention Grant
- Patent Title: Supplying hysteresis effect mitigated clock signals based on silicon-test characterized parameter
- Patent Title (中): 基于硅测试特征参数提供滞后效应减轻时钟信号
-
Application No.: US12847369Application Date: 2010-07-30
-
Publication No.: US08504866B2Publication Date: 2013-08-06
- Inventor: Arun Iyer , Bhawna Tomar , Animesh Jain , Krishna Sethupathy Leela
- Applicant: Arun Iyer , Bhawna Tomar , Animesh Jain , Krishna Sethupathy Leela
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Terrile, Cannatti, Chambers & Holland, LLP
- Agent Stephen A. Terrile
- Main IPC: G06F1/04
- IPC: G06F1/04
Abstract:
Embodiments of systems and methods are described for reducing the effects of hysteresis in the operation of data processing circuitry. In this embodiment of the invention, adaptive control circuitry is used to reduce the effects of hysteresis. The embodiment disclosed herein provides significant reduction in the effects of hysteresis and, therefore, a significant reduction in the amount of guard band needed to compensate for hysteresis effects in SOI processes and thereby improving the performance/power characteristics of the circuit.
Public/Granted literature
- US20120030500A1 Hysteresis Management in SOI Data Processing Circuits Public/Granted day:2012-02-02
Information query
