Invention Grant
- Patent Title: Apparatus for using metastability-hardened storage circuits in logic devices and associated methods
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Application No.: US13149774Application Date: 2011-05-31
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Publication No.: US08508254B2Publication Date: 2013-08-13
- Inventor: David Lewis , Jeffrey Christopher Chromczak , Ryan Fung
- Applicant: David Lewis , Jeffrey Christopher Chromczak , Ryan Fung
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Law Offices of Maximilian R. Peterson
- Main IPC: H03K19/00
- IPC: H03K19/00

Abstract:
An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.
Public/Granted literature
- US20110227625A1 APPARATUS FOR USING METASTABILITY-HARDENED STORAGE CIRCUITS IN LOGIC DEVICES AND ASSOCIATED METHODS Public/Granted day:2011-09-22
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