Invention Grant
US08524532B1 Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein
有权
集成电路封装，包括嵌入式功率级，其中第一场效应晶体管（FET）和第二FET电耦合在其中
- Patent Title: Integrated circuit package including an embedded power stage wherein a first field effect transistor (FET) and a second FET are electrically coupled therein
- Patent Title (中): 集成电路封装，包括嵌入式功率级，其中第一场效应晶体管（FET）和第二FET电耦合在其中
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Application No.: US13406257Application Date: 2012-02-27
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Publication No.: US08524532B1Publication Date: 2013-09-03
- Inventor: Rajeev Joshi
- Applicant: Rajeev Joshi
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Eugene C. Conser; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package.
Public/Granted literature
- US20130221442A1 EMBEDDED POWER STAGE MODULE Public/Granted day:2013-08-29
Information query
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