Metal-gate CMOS device and fabrication method thereof

Invention Grant

US08592271B2 Metal-gate CMOS device and fabrication method thereof 有权

Title translation: 金属栅CMOS器件及其制造方法

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Patent Title: Metal-gate CMOS device and fabrication method thereof
Patent Title (中): 金属栅CMOS器件及其制造方法
Application No.: US13895376

Application Date: 2013-05-16
Publication No.: US08592271B2

Publication Date: 2013-11-26
Inventor: Shih-Hung Tsai , Wen-Tai Chiang , Chen-Hua Tsai , Cheng-Tzung Tsai
Applicant: United Microelectronics Corp.
Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
Assignee: United Microelectronics Corp.
Current Assignee: United Microelectronics Corp.
Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
Agent Winston Hsu; Scott Margo
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L21/70

Metal-gate CMOS device and fabrication method thereof

Abstract:

A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Abstract(Chinese):

一种制造金属栅CMOS器件的方法。提供其上具有第一区域和第二区域的基板。第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。第一区域用密封层掩蔽。此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。

Public/Granted literature

US20130252387A1 METAL-GATE CMOS DEVICE AND FABRICATION METHOD THEREOF Public/Granted day:2013-09-26

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS