A cache is configured to have a first cache line allocation policy for a memory address. An instruction associated with the memory address is received and a second cache line allocation policy is determined based on the instruction. The cache is reconfigured to have the second cache line allocation policy in response to receiving the instruction. A data processor includes processor core to receive and execute an instruction associated with a memory address, a cache including a plurality of cache lines, and a cache allocation module to determine a cache line allocation policy based on the instruction and to reconfigure the cache to have the cache line allocation policy for execution of the instruction at the processor core.