Invention Grant
US08667493B2 Memory-controller-parallelism-aware scheduling for multiple memory controllers
有权
用于多个存储器控制器的内存控制器 - 并行性感知调度
- Patent Title: Memory-controller-parallelism-aware scheduling for multiple memory controllers
- Patent Title (中): 用于多个存储器控制器的内存控制器 - 并行性感知调度
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Application No.: US12775643Application Date: 2010-05-07
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Publication No.: US08667493B2Publication Date: 2014-03-04
- Inventor: Jaewoong Chung , Debarshi Chatterjee
- Applicant: Jaewoong Chung , Debarshi Chatterjee
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Abel Law Group, LLP
- Main IPC: G06F9/44
- IPC: G06F9/44 ; G06F12/08

Abstract:
Some embodiments of a processing system implement a memory-controller-parallelism-aware scheduling technique. In at least one embodiment of the invention, a method of operating a processing system includes scheduling a memory request requested by a thread of a plurality of threads executing on at least one processor according to thread priority information associated with the plurality of threads. The thread priority information is based on a maximum of a plurality of local memory bandwidth usage indicators for each thread of the plurality of threads. Each of the plurality of local memory bandwidth usage indicators for each thread corresponds to a respective memory controller of a plurality of memory controllers.
Public/Granted literature
- US20110276972A1 MEMORY-CONTROLLER-PARALLELISM-AWARE SCHEDULING FOR MULTIPLE MEMORY CONTROLLERS Public/Granted day:2011-11-10
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