Invention Grant
US08735220B2 Method for positioning chips during the production of a reconstituted wafer
有权
在重新制造的晶片生产期间定位芯片的方法
- Patent Title: Method for positioning chips during the production of a reconstituted wafer
- Patent Title (中): 在重新制造的晶片生产期间定位芯片的方法
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Application No.: US13377109Application Date: 2010-06-14
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Publication No.: US08735220B2Publication Date: 2014-05-27
- Inventor: Christian Val
- Applicant: Christian Val
- Applicant Address: FR Buc
- Assignee: 3D Plus
- Current Assignee: 3D Plus
- Current Assignee Address: FR Buc
- Agency: Baker Hostetler LLP
- Priority: FR0902871 20090612
- International Application: PCT/EP2010/058277 WO 20100614
- International Announcement: WO2010/142804 WO 20101216
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the chips with their RDL layer and the mini RDL being the re-built wafer.
Public/Granted literature
- US20120094439A1 Method for Positioning Chips During the Production of a Reconstituted Wafer Public/Granted day:2012-04-19
Information query
IPC分类: