Invention Grant
US08742490B2 Vertical power transistor die packages and associated methods of manufacturing 有权
垂直功率晶体管管芯封装及相关制造方法

Vertical power transistor die packages and associated methods of manufacturing
Abstract:
The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.
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