Invention Grant
- Patent Title: Method for fabricating strained-silicon CMOS transistor
- Patent Title (中): 制造应变硅CMOS晶体管的方法
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Application No.: US12959393Application Date: 2010-12-03
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Publication No.: US08828815B2Publication Date: 2014-09-09
- Inventor: Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
- Applicant: Pei-Yu Chou , Shih-Fang Tzou , Jiunn-Hsiung Liao
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78

Abstract:
First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.
Public/Granted literature
- US20110076814A1 METHOD FOR FABRICATING STRAINED-SILICON CMOS TRANSISTOR Public/Granted day:2011-03-31
Information query
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