Invention Grant
- Patent Title: Probe pad design for 3DIC package yield analysis
- Patent Title (中): 探针垫设计，用于3DIC封装产量分析
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Application No.: US13272004Application Date: 2011-10-12
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Publication No.: US08878182B2Publication Date: 2014-11-04
- Inventor: Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
- Applicant: Tzu-Yu Wang , Chen-Hua Yu , Shin-Puu Jeng , Shang-Yun Hou , Hsien-Pin Hu , Wei-Cheng Wu , Li-Han Hsu , Meng-Han Lee
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/58
- IPC: H01L23/58 ; H01L21/66 ; H01L23/498 ; H01L23/538 ; H01L23/00 ; H01L25/065 ; H01L23/31
Abstract:
An interposer includes a first surface on a first side of the interposer and a second surface on a second side of the interposer, wherein the first and the second sides are opposite sides. A first probe pad is disposed at the first surface. An electrical connector is disposed at the first surface, wherein the electrical connector is configured to be used for bonding. A through-via is disposed in the interposer. Front-side connections are disposed on the first side of the interposer, wherein the front-side connections electrically couple the through-via to the probe pad.
Public/Granted literature
- US20130092935A1 Probe Pad Design for 3DIC Package Yield Analysis Public/Granted day:2013-04-18
Information query
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