Invention Grant
US08941175B2 Power array with staggered arrangement for improving on-resistance and safe operating area
有权
功率阵列具有交错布置,用于改善导通电阻和安全工作区域
- Patent Title: Power array with staggered arrangement for improving on-resistance and safe operating area
- Patent Title (中): 功率阵列具有交错布置,用于改善导通电阻和安全工作区域
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Application No.: US13918994Application Date: 2013-06-17
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Publication No.: US08941175B2Publication Date: 2015-01-27
- Inventor: Wei-Lin Chen , Ke-Feng Lin , Chiu-Ling Lee , Chiu-Te Lee , Chih-Chung Wang , Hsuan-Po Liao
- Applicant: United Microelectronics Corp.
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/772 ; H01L27/088 ; H01L27/092

Abstract:
A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.
Public/Granted literature
- US20140367789A1 POWER ARRAY WITH STAGGERED ARRANGEMENT FOR IMPROVING ON-RESISTANCE AND SAFE OPERATING AREA Public/Granted day:2014-12-18
Information query
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