Invention Grant
- Patent Title: Debug architecture
- Patent Title (中): 调试架构
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Application No.: US13938065Application Date: 2013-07-09
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Publication No.: US09003232B2Publication Date: 2015-04-07
- Inventor: Andrew Brian Thomas Hopkins
- Applicant: UltraSoC Technologies Ltd.
- Applicant Address: GB Cambridge
- Assignee: Ultrasoc Technologies Ltd.
- Current Assignee: Ultrasoc Technologies Ltd.
- Current Assignee Address: GB Cambridge
- Agency: Haynes Deffel & Wolfeld LLP
- Agent Warren S. Wolfeld
- Priority: GBGB1212178.6 20120709
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/263 ; G06F11/267

Abstract:
Roughly described, a method of sending a message from a source unit to a destination unit both forming part of a hierarchical debug architecture on a chip, the units in the hierarchy using a protocol in which each unit has an internal address which is the same base address, and in which each unit addresses other units using addresses derivable relative to that unit's internal address given positions of other units in the hierarchy, comprising: the source unit in a first level of the hierarchy sending a message comprising a destination address of the destination unit, the destination address being relative to the source unit's internal address, and an intermediate unit in a second level of the hierarchy: adding an offset to the destination address to form a rebased destination address, being relative to the intermediate unit's internal address, and routing the rebased message onto the destination unit.
Public/Granted literature
- US20140013161A1 DEBUG ARCHITECTURE Public/Granted day:2014-01-09
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