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公开(公告)号：US09928361B2
公开(公告)日：2018-03-27
申请号：US15617953
申请日：2017-06-08
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US20140013421A1
公开(公告)日：2014-01-09
申请号：US13938098
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC: G06F21/44
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
Abstract translation: 大致描述了一种限制调试控制器访问集成电路芯片上的架构的方法，所述调试架构包括访问控制器，多个外围电路和共享集线器，共享集线器可由访问控制器访问，以及 所述多个外围电路，所述方法包括：在所述访问控制器处，认证所述调试控制器; 在访问控制器处，在认证之后向调试控制器分配一组访问权限，授予调试控制器部分访问调试体系结构的一组访问权限; 并且在分配了一组访问权限之后，允许调试控制器访问该组访问权限所允许的调试架构。
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公开(公告)号：US20140013157A1
公开(公告)日：2014-01-09
申请号：US13938053
申请日：2013-07-09
Applicant: UltraSoc Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins
IPC: G06F11/27
CPC classification number: G06F11/2205 , B01J23/04 , B01J38/485 , G06F11/3632 , G06F11/3656
Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
Abstract translation: 粗略地描述，集成电路芯片包括多个外围电路，每个外围电路连接到相应的调试单元，相应的调试单元被配置为产生该外围电路的调试信息; 以及多个单独存储器，用于接收调试信息，存储调试信息并输出调试信息; 其中响应于单个触发信号，所述调试单元被配置为将其生成的调试信息流传送到所述多个单独的存储器; 并且其中所述多个单独存储器中的每一个被配置为以比它输出调试信息更高的流速度接收调试信息。
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公开(公告)号：US20140013145A1
公开(公告)日：2014-01-09
申请号：US13938077
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins
IPC: G06F1/26
CPC classification number: G01R31/31705 , G01R31/31721 , G06F1/24 , G06F1/26 , G06F1/30 , G06F1/32 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3246 , G06F1/325 , G06F1/3287 , G06F11/263 , G06F11/267 , G06F11/36 , G06F11/362 , G06F11/3636 , G06F11/3648 , G06F11/3656 , G06F15/7807
Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.
Abstract translation: 粗略地描述了一种对集成电路芯片的一部分断电的方法，该集成电路芯片的部分包括多个外围电路，每个外围电路连接到相应的调试单元，该方法包括：在断电之前， 从所述调试单元的每个调试单元的配置信息中提取所述调试单元的配置信息; 在集成电路芯片的部分断电期间将调试单元的配置信息存储在集成电路芯片上的存储器中; 并且在上电时，在恢复该调试单元和连接到该调试单元的外围电路的操作之前将每个调试单元的配置信息恢复到该调试单元。
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公开(公告)号：US10132863B2
公开(公告)日：2018-11-20
申请号：US14843745
申请日：2015-09-02
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins
IPC: G06F1/32 , G06F1/26 , G06F1/00 , G06F9/44 , G01R31/28 , G01R31/317 , G06F1/24 , G06F1/30 , G06F11/36 , G06F11/263 , G06F11/267 , G06F15/78
Abstract: Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.
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Patent Agency Ranking
公开(公告)号：US09927486B2
公开(公告)日：2018-03-27
申请号：US15241805
申请日：2016-08-19
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter Mcdonald-Maier
CPC classification number: G01R31/2884 , G01R31/31705 , G01R31/31719 , G06F11/27 , G06F11/348 , G06F21/44 , G06F21/62 , G06F21/85 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US09218258B2
公开(公告)日：2015-12-22
申请号：US13938053
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins
CPC classification number: G06F11/2205 , B01J23/04 , B01J38/485 , G06F11/3632 , G06F11/3656
Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit, the respective debug unit configured to generate debug information of that peripheral circuit; and a plurality of separate stores for receiving debug information, storing debug information, and outputting debug information; wherein in response to a single trigger signal, the debug units are configured to stream their generated debug information to the plurality of separate stores; and wherein each of the plurality of separate stores is configured to receive debug information at a higher stream rate than it outputs debug information.
Abstract translation: 粗略地描述，集成电路芯片包括多个外围电路，每个外围电路连接到相应的调试单元，相应的调试单元被配置为产生该外围电路的调试信息; 以及多个单独存储器，用于接收调试信息，存储调试信息并输出调试信息; 其中响应于单个触发信号，所述调试单元被配置为将其生成的调试信息流传送到所述多个单独的存储器; 并且其中所述多个单独存储器中的每一个被配置为以比它输出调试信息更高的流速度接收调试信息。
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8.发明授权Prioritising event data over configuration data in a single interface in a SoC/debug architecture 有权在SoC /调试架构中的单个接口中对配置数据进行优先级排序公开(公告)号：US09032109B2
公开(公告)日：2015-05-12
申请号：US13938046
申请日：2013-07-09
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins
CPC classification number: G06F9/4411 , G06F11/3636 , G06F11/3656 , G06F15/7807
Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit; a shared hub; and between each respective debug unit and the shared hub, a single physical interface configured to transport both configuration data and event data, wherein the interface is configured such that if an event occurs while the interface is transporting configuration data, the interface interrupts the transport of the configuration data in order to transport the event data.
Abstract translation: 粗略地描述，集成电路芯片包括多个外围电路，每个外围电路连接到相应的调试单元; 共享中心 并且在每个相应的调试单元和共享集线器之间，被配置为传送配置数据和事件数据的单个物理接口，其中所述接口被配置为使得如果在所述接口正在传输配置数据的情况下发生事件，则所述接口中断 配置数据为了传输事件数据。
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公开(公告)号：US20170277883A1
公开(公告)日：2017-09-28
申请号：US15617953
申请日：2017-06-08
Applicant: UltraSoC Technologies Ltd.
Inventor： Andrew Brian Thomas Hopkins , Arnab Banerjee , Stephen John Barlow , Klaus Dieter McDonald-Maier
IPC: G06F21/44 , G01R31/317 , G06F21/62 , G06F11/34
CPC classification number: G06F21/44 , G01R31/31705 , G01R31/31719 , G06F11/348 , G06F21/62 , G06F2201/835 , G06F2201/86 , G06F2201/88
Abstract: Roughly described, a method of restricting access of a debug controller to debug architecture on an integrated circuit chip, the debug architecture comprising an access controller, a plurality of peripheral circuits, and a shared hub, the shared hub being accessible by the access controller and the plurality of peripheral circuits, the method comprising: at the access controller, authenticating the debug controller; at the access controller, following authentication, assigning to the debug controller a set of access rights, the set of access rights granting the debug controller partial access to the debug architecture; and after assigning the set of access rights, allowing the debug controller access to the debug architecture as allowed by the set of access rights.
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公开(公告)号：US09632138B2
公开(公告)日：2017-04-25
申请号：US14879597
申请日：2015-10-09
Applicant: UltraSoC Technologies Ltd.
IPC: G01R31/317 , G01R31/3177
CPC classification number: G01R31/31705 , G01R31/31725 , G01R31/31727 , G01R31/3177
Abstract: A method of functionality testing system circuitry on an integrated circuit chip, the system circuitry comprising a plurality of sub-circuits and the integrated circuit chip further comprising debugging circuitry, the debugging circuitry comprising variability circuitry. The method comprises: at the system circuitry, performing a function by the sub-circuits performing concurrent actions; at the variability circuitry, altering relative timing of the concurrent actions so as to increase the likelihood of one or more errors in the system circuitry's performance of the function; and at the debugging circuitry, recording one or more errors in the system circuitry's performance of the function.
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