Invention Grant
- Patent Title: Methods and systems for logic device defect tolerant redundancy
- Patent Title (中): 逻辑器件缺陷容错冗余的方法和系统
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Application No.: US13598390Application Date: 2012-08-29
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Publication No.: US09037931B2Publication Date: 2015-05-19
- Inventor: Angel Socarras
- Applicant: Angel Socarras
- Applicant Address: US CA Sunnyvale
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: Volpe and Koenig, P.C.
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3185 ; G01R31/3183 ; G01R31/3177 ; G11C29/00

Abstract:
Provided is an apparatus including a scheduler and a plurality of logic devices coupled to the scheduler, each including a defect indicator. The scheduler determines whether one or more of the logic devices is defective based upon its respective defect indicator. The scheduler intentionally omits sending workloads to the disabled logic units, and thus enables the device to be functional albeit at a lower performance or in a differently performing product.
Public/Granted literature
- US20130166974A1 METHODS AND SYSTEMS FOR LOGIC DEVICE DEFECT TOLERANT REDUNDANCY Public/Granted day:2013-06-27
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