Invention Grant
- Patent Title: Edge coupling of semiconductor dies
- Patent Title (中): 半导体管芯的边缘耦合
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Application No.: US14017867Application Date: 2013-09-04
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Publication No.: US09087702B2Publication Date: 2015-07-21
- Inventor: Tim V. Pham , Michael B. McShane , Perry H. Pelley , Andrew C. Russell , James R. Guajardo
- Applicant: Freescale Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Agency: Fogarty, L.L.C.
- Agent Luiz von Paumgartten
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/00

Abstract:
Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
Public/Granted literature
- US20150061097A1 EDGE COUPLING OF SEMICONDUCTOR DIES Public/Granted day:2015-03-05
Information query
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