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公开(公告)号：US10002653B2
公开(公告)日：2018-06-19
申请号：US14525347
申请日：2014-10-28
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
CPC classification number: G11C8/06 , G06F13/4208 , G11C7/00 , G11C8/12 , H01L25/0657 , H01L25/50 , H01L2924/0002 , H01L2924/00
Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.
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公开(公告)号：US20150208510A1
公开(公告)日：2015-07-23
申请号：US14158310
申请日：2014-01-17
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
CPC classification number: H05K1/181 , G11C5/063 , H01L23/5384 , H01L23/5385 , H01L25/0652 , H01L25/10 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/1434 , H05K3/3415 , H05K2201/097 , H05K2201/10159 , H05K2201/10378 , H05K2201/10545 , Y02P70/611 , H01L2924/014 , H01L2924/00014
Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.
Abstract translation: 低剖面条双列直插式存储器模块（200）包括：被动中插支撑结构（90），其具有形成在相对的顶表面和底表面之间的图案化开口（91-97）;多个存储芯片（D1-D8） 顶表面和底表面以及垂直焊球导体（98），其延伸穿过图案化的开口以电连接多个存储器芯片，其中每个存储器芯片具有面向无源插入器结构的附接表面和水平导体的图案化阵列（例如， ，82-86），其形成在所述附接表面上，所述接触垫电连接到所述多个垂直导体，以限定电连接到所述第一和第二多个存储器管芯中的每个存储器管芯的至少一个总线导体。
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公开(公告)号：US09087702B2
公开(公告)日：2015-07-21
申请号：US14017867
申请日：2013-09-04
Applicant: Freescale Semiconductor, Inc.
Inventor： Tim V. Pham , Michael B. McShane , Perry H. Pelley , Andrew C. Russell , James R. Guajardo
CPC classification number: H01L24/06 , H01L23/13 , H01L23/4951 , H01L23/49541 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/89 , H01L25/0652 , H01L25/0657 , H01L2224/02375 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/1012 , H01L2224/13022 , H01L2224/16105 , H01L2224/16106 , H01L2224/16137 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/17155 , H01L2224/17181 , H01L2224/29036 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73203 , H01L2224/8114 , H01L2224/81191 , H01L2224/81815 , H01L2225/06527 , H01L2225/06551 , H01L2225/06572 , H01L2225/06575 , H01L2225/06593 , H01L2924/12042 , H01L2924/15787 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
Abstract: Edge coupling of semiconductor dies. In some embodiments, a semiconductor device may include a first semiconductor die, a second semiconductor die disposed in a face-to-face configuration with respect to the first semiconductor die, and an interposer arranged between the first semiconductor and second semiconductor dies, the interposer having an edge detent configured to allow an electrical coupling between the first and second semiconductor dies. In other embodiments, a method may include coupling a first semiconductor die to a surface of an interposer where an edge of the interposer includes detents and the first semiconductor die includes a first pad aligned with a first detent, coupling a second semiconductor die to an opposite surface of the interposer where the first and second semiconductor dies are in a face-to-face configuration and the second semiconductor die includes a second pad aligned with a second detent, and coupling the first and second pads together.
Abstract translation: 半导体管芯的边缘耦合。 在一些实施例中，半导体器件可以包括第一半导体管芯，相对于第一半导体管芯以面对面配置设置的第二半导体管芯，以及布置在第一半导体和第二半导体管芯之间的插入器，插入器 具有构造成允许第一和第二半导体管芯之间的电耦合的边缘制动器。 在其他实施例中，一种方法可以包括将第一半导体管芯耦合到插入器的表面，其中插入器的边缘包括制动器，并且第一半导体管芯包括与第一制动器对准的第一焊盘，将第二半导体管芯耦合到相反的 其中第一和第二半导体管芯是面对面配置的内插器表面，并且第二半导体管芯包括与第二制动器对准的第二焊盘，并将第一和第二焊盘耦合在一起。
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公开(公告)号：US10177052B2
公开(公告)日：2019-01-08
申请号：US14247823
申请日：2014-04-08
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.
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公开(公告)号：US20160118095A1
公开(公告)日：2016-04-28
申请号：US14525347
申请日：2014-10-28
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
CPC classification number: G11C8/06 , G06F13/4208 , G11C7/00 , G11C8/12 , H01L25/0657 , H01L25/50 , H01L2924/0002 , H01L2924/00
Abstract: The dies of a stacked die integrated circuit (IC) employ the address bus to indicate the particular die, or set of dies, targeted by data on a data bus. During manufacture of the stacked die IC, the IC is programmed with information indicating a width of the address bus. During operation, each die addresses the other dies with addresses having the corresponding width based on this programmed information.
Abstract translation: 堆叠管芯集成电路（IC）的管芯使用地址总线来指示由数据总线上的数据所针对的特定管芯或一组管芯。 在堆叠管芯IC的制造期间，IC被编程有指示地址总线的宽度的信息。 在操作期间，每个管芯基于该编程的信息来寻址具有相应宽度的地址的其它管芯。
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Patent Agency Ranking
公开(公告)号：US09480161B2
公开(公告)日：2016-10-25
申请号：US14158310
申请日：2014-01-17
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
IPC: H05K1/18 , H05K1/11 , H01L23/538 , H01L25/10 , H01L25/065 , H05K3/34 , G11C5/06
CPC classification number: H05K1/181 , G11C5/063 , H01L23/5384 , H01L23/5385 , H01L25/0652 , H01L25/10 , H01L25/105 , H01L25/50 , H01L2224/131 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/1434 , H05K3/3415 , H05K2201/097 , H05K2201/10159 , H05K2201/10378 , H05K2201/10545 , Y02P70/611 , H01L2924/014 , H01L2924/00014
Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.
Abstract translation: 低剖面条双列直插式存储器模块（200）包括：被动中插支撑结构（90），其具有形成在相对的顶表面和底表面之间的图案化开口（91-97）;多个存储芯片（D1-D8） 顶表面和底表面以及垂直焊球导体（98），其延伸穿过图案化的开口以电连接多个存储器芯片，其中每个存储器芯片具有面向无源插入器结构的附接表面和水平导体的图案化阵列（例如， ，82-86），其形成在所述附接表面上，所述接触垫电连接到所述多个垂直导体，以限定电连接到所述第一和第二多个存储器管芯中的每个存储器管芯的至少一个总线导体。
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公开(公告)号：US20150287653A1
公开(公告)日：2015-10-08
申请号：US14247823
申请日：2014-04-08
Applicant: Freescale Semiconductor, Inc.
Inventor： Perry H. Pelley , Michael B. McShane , Tim V. Pham
IPC: H01L21/66 , H01L25/00 , H01L25/065
CPC classification number: H01L22/22 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/13111 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06596 , H01L2924/14 , H01L2924/1436 , H01L2924/15311 , H01L2224/81 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029
Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.
Abstract translation: 测试堆叠管芯IC的管芯，并且响应于检测到其中一个管芯处的缺陷，识别缺陷的类型。 如果缺陷被识别为在芯片本身可修复的有缺陷的模块，则使用芯片的冗余模块来代替有缺陷模块的功能。 如果将缺陷识别为不可修复的缺陷，则使用芯片堆叠中的替换裸片来代替有缺陷的裸片的功能。
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公开(公告)号：US09070657B2
公开(公告)日：2015-06-30
申请号：US14048721
申请日：2013-10-08
Applicant: Freescale Semiconductor, Inc.
Inventor： Tim V. Pham , Derek S. Swanson , Trent S. Uehling
IPC: H01L23/36 , H01L25/065 , H01L25/00
CPC classification number: H01L23/36 , H01L21/561 , H01L23/367 , H01L23/3672 , H01L23/49827 , H01L23/50 , H01L25/0657 , H01L25/50 , H01L2924/15311
Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
Abstract translation: 集成电路封装包括具有与散热部一体形成的导热部的基板。 第一和第二集成电路管芯安装在衬底的导热部分的相对两侧。 第一和第二集成电路管芯可以各自被封装成倒装芯片配置。 可以通过形成在基板的导热部分中的开口形成第一和第二集成电路管芯上的接触焊盘之间的电连接。 散热部分可以位于从第一和第二集成电路管芯之间的位置的外部，使得其将热量从集成电路封装件散发到周围环境中。
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公开(公告)号：US20150097280A1
公开(公告)日：2015-04-09
申请号：US14048721
申请日：2013-10-08
Applicant: Freescale Semiconductor, Inc.
Inventor： Tim V. Pham , Derek S. Swanson , Trent S. Uehling
IPC: H01L23/36 , H01L25/00 , H01L25/065
CPC classification number: H01L23/36 , H01L21/561 , H01L23/367 , H01L23/3672 , H01L23/49827 , H01L23/50 , H01L25/0657 , H01L25/50 , H01L2924/15311
Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.
Abstract translation: 集成电路封装包括具有与散热部一体形成的导热部的基板。 第一和第二集成电路管芯安装在衬底的导热部分的相对两侧。 第一和第二集成电路管芯可以各自被封装成倒装芯片配置。 可以通过形成在基板的导热部分中的开口形成第一和第二集成电路管芯上的接触焊盘之间的电连接。 散热部分可以位于从第一和第二集成电路管芯之间的位置的外部，使得其将热量从集成电路封装件散发到周围环境中。
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公开(公告)号：US20150069624A1
公开(公告)日：2015-03-12
申请号：US14024742
申请日：2013-09-12
Applicant: Freescale Semiconductor, Inc.
Inventor： Tim V. Pham , Fonzell D. Martin , Derek S. Swanson
CPC classification number: H01L25/0652 , H01L24/94 , H01L24/97 , H01L25/071 , H01L25/105 , H01L25/112 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/16245 , H01L2224/17181 , H01L2224/32145 , H01L2224/73204 , H01L2224/81815 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06555 , H01L2225/10 , H01L2924/14 , H01L2924/1433 , H01L2924/1434 , H01L2924/15311 , H01L2224/81 , H01L2924/00
Abstract: Recessed semiconductor die stacks. In some embodiments, a semiconductor device includes a first die including an active side and a back side, the back side including a non-recessed portion thicker than a recessed portion, the recessed portion including one or more through-die vias on a recessed surface; and a second die located in the recessed portion, the second die including an active side facing the recessed surface of the first die and coupled thereto through the one or more through-die vias. In another embodiment, a method includes creating a recess on a first die having a first thickness, the recess having a depth smaller than the first thickness; coupling a second die having a second thickness greater than the depth to the recess; and reducing the thickness of the second die by an amount equal to or greater than a difference between the second thickness and the depth.
Abstract translation: 嵌入式半导体管芯堆叠。 在一些实施例中，半导体器件包括包括有源侧和后侧的第一管芯，该背面包括比凹部更厚的非凹部，该凹部包括在凹陷表面上的一个或多个贯通孔通孔 ; 以及位于所述凹陷部分中的第二模具，所述第二模具包括面向所述第一模具的凹陷表面的活动侧并且通过所述一个或多个通孔通孔而与其连接。 在另一个实施例中，一种方法包括在第一模具上形成具有第一厚度的凹槽，凹部具有小于第一厚度的深度; 将具有大于所述凹部的深度的第二厚度的第二模具联接到所述凹部; 并且将第二模具的厚度减小等于或大于第二厚度和深度之间的差值。
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