Invention Grant
- Patent Title: Low-k interconnect structures with reduced RC delay
- Patent Title (中): 具有降低RC延迟的低k互连结构
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Application No.: US11585610Application Date: 2006-10-24
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Publication No.: US09087877B2Publication Date: 2015-07-21
- Inventor: Chung-Chi Ko , Ting-Yu Shen , Keng-Chu Lin , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
- Applicant: Chung-Chi Ko , Ting-Yu Shen , Keng-Chu Lin , Chia-Cheng Chou , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768

Abstract:
A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.
Public/Granted literature
- US20080096380A1 Low-k interconnect structures with reduced RC delay Public/Granted day:2008-04-24
Information query
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