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US09088292B1 Clocking scheme for reconfigurable wideband analog-to-digital converter 有权
可重配置宽带模数转换器的时钟方案

Clocking scheme for reconfigurable wideband analog-to-digital converter
Abstract:
A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.
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