Invention Grant
- Patent Title: Parallel bit interleaver
- Patent Title (中): 并行位交织器
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Application No.: US14115760Application Date: 2012-05-18
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Publication No.: US09100049B2Publication Date: 2015-08-04
- Inventor: Mihail Petrov
- Applicant: Mihail Petrov
- Applicant Address: JP Osaka
- Assignee: PANASONIC CORPORATION
- Current Assignee: PANASONIC CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004127 20110518
- International Application: PCT/JP2012/003264 WO 20120518
- International Announcement: WO2012/157284 WO 20121122
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H03M13/25 ; H03M13/27 ; H03M13/29 ; H03M13/35 ; H04L1/00 ; H04L1/06

Abstract:
A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N′/M folding sections (N′ being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N′/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.
Public/Granted literature
- US20140075271A1 PARALLEL BIT INTERLEAVER Public/Granted day:2014-03-13
Information query
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