Invention Grant
US09119313B2 Package substrate with high density interconnect design to capture conductive features on embedded die
有权
封装衬底采用高密度互连设计,以捕获嵌入式裸片上的导电特性
- Patent Title: Package substrate with high density interconnect design to capture conductive features on embedded die
- Patent Title (中): 封装衬底采用高密度互连设计,以捕获嵌入式裸片上的导电特性
-
Application No.: US13870874Application Date: 2013-04-25
-
Publication No.: US09119313B2Publication Date: 2015-08-25
- Inventor: Chong Zhang , Stefanie M. Lotz , Islam A. Salama
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt PC
- Main IPC: H05K1/18
- IPC: H05K1/18 ; H05K1/11 ; H05K3/40

Abstract:
Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed.
Public/Granted literature
- US20140321091A1 PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE Public/Granted day:2014-10-30
Information query