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US09130017B2 Methods for forming interconnect structures of integrated circuits 有权
形成集成电路互连结构的方法

Methods for forming interconnect structures of integrated circuits
Abstract:
A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.
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