Invention Grant
- Patent Title: Methods for forming interconnect structures of integrated circuits
- Patent Title (中): 形成集成电路互连结构的方法
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Application No.: US13220245Application Date: 2011-08-29
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Publication No.: US09130017B2Publication Date: 2015-09-08
- Inventor: Po-Cheng Shih , Chung-Chi Ko , Keng-Chu Lin
- Applicant: Po-Cheng Shih , Chung-Chi Ko , Keng-Chu Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L21/311 ; H01L21/02

Abstract:
A method includes forming a hard mask over a low-k dielectric layer, and patterning the hard mask to form an opening. A stress tuning layer is formed over the low-k dielectric layer and in physical contact with the hard mask. The stress tuning layer has an inherent stress, wherein the inherent stress is a near-zero stress or a tensile stress. The low-k dielectric layer is etched to form a trench aligned to the opening, wherein the step of etching is performed using the hard mask as an etching mask.
Public/Granted literature
- US20130052818A1 Methods for Forming Interconnect Structures of Integrated Circuits Public/Granted day:2013-02-28
Information query
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