Invention Grant
US09130056B1 Bi-layer wafer-level underfill mask for wafer dicing and approaches for performing wafer dicing
有权
用于晶片切割的双层晶片级底部填充掩模和用于执行晶片切割的方法
- Patent Title: Bi-layer wafer-level underfill mask for wafer dicing and approaches for performing wafer dicing
- Patent Title (中): 用于晶片切割的双层晶片级底部填充掩模和用于执行晶片切割的方法
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Application No.: US14506455Application Date: 2014-10-03
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Publication No.: US09130056B1Publication Date: 2015-09-08
- Inventor: James M. Holden , James S. Papanu , Wei-Sheng Lei , Brad Eaton , Ajay Kumar
- Applicant: James M. Holden , James S. Papanu , Wei-Sheng Lei , Brad Eaton , Ajay Kumar
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely Sokoloff Taylor Zafman LLP
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L21/46 ; H01L21/301 ; H01L21/82 ; H01L21/56 ; H01L21/3065
Abstract:
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having integrated circuits on a front side thereof involves laminating a pre-patterned bi-layer wafer-level underfill material stack on the integrated circuits of the semiconductor wafer. The pre-patterned bi-layer wafer-level underfill material stack has regions corresponding to the integrated circuits and gaps corresponding to dicing streets between the integrated circuits. The method also involves plasma etching to form trenches in the semiconductor wafer in alignment with the dicing streets to singulate the integrated circuits. An upper layer of the pre-patterned bi-layer wafer-level underfill material stack protects the integrated circuits during the plasma etching.
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