Invention Grant
- Patent Title: Compliant printed circuit wafer level semiconductor package
- Patent Title (中): 符合印刷电路晶圆级半导体封装
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Application No.: US13318200Application Date: 2010-05-27
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Publication No.: US09136196B2Publication Date: 2015-09-15
- Inventor: James Rathburn
- Applicant: James Rathburn
- Applicant Address: US MN Maple Grove
- Assignee: HSIO TECHNOLOGIES, LLC
- Current Assignee: HSIO TECHNOLOGIES, LLC
- Current Assignee Address: US MN Maple Grove
- Agency: Stoel Rives LLP
- International Application: PCT/US2010/036288 WO 20100527
- International Announcement: WO2010/141297 WO 20101209
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/31 ; H01L21/683 ; H01L25/065 ; H01L23/525 ; H01L23/00

Abstract:
A wafer-level package for semiconductor devices and a method for making the package. At least one dielectric layer is selectively printed on at least a portion of the semiconductor devices creating first recesses aligned with a plurality of electrical terminals on the semiconductor devices. A conductive material is printed in the first recesses to form contact members on the semiconductor devices. At least one dielectric layer is selectively printed to create a plurality of second recesses corresponding to a target circuit geometry. A conductive material is printed in at least a portion of the second recesses to create a circuit geometry. The circuit geometry includes a plurality of exposed terminals adapted to electrically couple to another circuit member. The wafer is diced to provide a plurality of discrete packaged semiconductor devices.
Public/Granted literature
- US20120056332A1 COMPLIANT PRINTED CIRCUIT WAFER LEVEL SEMICONDUCTOR PACKAGE Public/Granted day:2012-03-08
Information query
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