Invention Grant
- Patent Title: Etch process for reducing directed self assembly pattern defectivity using direct current positioning
- Patent Title (中): 使用直流定位减少定向自组装图案缺陷的蚀刻工艺
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Application No.: US14018329Application Date: 2013-09-04
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Publication No.: US09153457B2Publication Date: 2015-10-06
- Inventor: Vidhya Chakrapani , Akiteru Ko , Kaushik A. Kumar
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Wood, Herron & Evans, LLP
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L21/311 ; H01L21/033 ; H01L21/67

Abstract:
A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process.
Public/Granted literature
- US20140370718A1 ETCH PROCESS FOR REDUCING DIRECTED SELF ASSEMBLY PATTERN DEFECTIVITY USING DIRECT CURRENT POSITIONING Public/Granted day:2014-12-18
Information query
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