Invention Grant
US09154154B2 Method and system for a low input voltage low impedance termination stage for current inputs
有权
用于电流输入的低输入电压低阻抗终端级的方法和系统
- Patent Title: Method and system for a low input voltage low impedance termination stage for current inputs
- Patent Title (中): 用于电流输入的低输入电压低阻抗终端级的方法和系统
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Application No.: US14471587Application Date: 2014-08-28
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Publication No.: US09154154B2Publication Date: 2015-10-06
- Inventor: Rajesh Zele , Gaurav Chandra
- Applicant: Maxlinear, Inc.
- Applicant Address: US CA Carlsbad
- Assignee: Maxlinear, Inc.
- Current Assignee: Maxlinear, Inc.
- Current Assignee Address: US CA Carlsbad
- Agency: McAndrews, Held & Malloy
- Main IPC: H03M1/66
- IPC: H03M1/66 ; H03M1/70

Abstract:
Methods and systems for a low input voltage low impedance termination stage for current inputs may include, in a semiconductor die, generating an output current proportional to an input signal, where the output current is generated by an output stage that may include a pair of input cascode transistors and at least one pair of stacked output transistors. A source-follower feedback path for the input cascode transistors may include a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground. A current source may be coupled to the drain of the first of the input cascode transistors. The supply voltage may be coupled to the stacked output transistors via a load resistor.
Public/Granted literature
- US20150061910A1 METHOD AND SYSTEM FOR A LOW INPUT VOLTAGE LOW IMPEDANCE TERMINATION STAGE FOR CURRENT INPUTS Public/Granted day:2015-03-05
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