Invention Grant
US09165906B2 High performance package on package 有权
高性能封装封装

High performance package on package
Abstract:
A microelectronic assembly can include a first package comprising a processor and a second package electrically connected to the first package. The second package can include two or more microelectronic elements each having memory storage array function and contacts at a respective element face, upper and lower opposite package faces, upper and lower terminals at the respective upper and lower package faces, and electrically conductive structure extending through the second package. At least portions of edges of respective microelectronic elements of the two or more microelectronic elements can be spaced apart from one another, so as to define a central region between the edges that does not overlie any of the element faces of the microelectronic elements of the second package. The electrically conductive structure can be aligned with the central region and can electrically connect the lower terminals with at least one of: the upper terminals or the contacts.
Public/Granted literature
Information query
Patent Agency Ranking
0/0