公开(公告)号：US20220139883A1

公开(公告)日：2022-05-05

申请号：US17577944

申请日：2022-01-18

Applicant: Invensas Corporation

Inventor： Javier A. DeLaCruz ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G06F15/78 ,  H01L23/532

Abstract: The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.

公开(公告)号：US11264357B1

公开(公告)日：2022-03-01

申请号：US17075489

申请日：2020-10-20

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/68

Abstract: Techniques and arrangements for performing exposure operations on a wafer utilizing both a stepper apparatus and an aligner apparatus. The exposure operations are performed with respect to large composite base dies, e.g., interposers, defined within the wafer, where the interposers will become a part of microelectronic devices by coupling with active dies or microchips. The composite base dies may be coupled to the active dies via “native interconnects” utilizing direct bonding techniques. The stepper apparatus may be used to perform exposure operations on active regions of the composite base dies to provide a fine pitch for the native interconnects, while the aligner apparatus may be used to perform exposure operations on inactive regions of the composite base dies to provide a coarse pitch for interfaces with passive regions of the composite base dies.

公开(公告)号：US20210327851A1

公开(公告)日：2021-10-21

申请号：US17362712

申请日：2021-06-29

Applicant: Invensas Corporation

Inventor： Javier A. Delacruz ,  Belgacem Haba

IPC: H01L25/065 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H05K1/02 ,  H05K3/46 ,  H01L23/538

Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.

公开(公告)号：US10991676B2

公开(公告)日：2021-04-27

申请号：US16814175

申请日：2020-03-10

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Javier A. Delacruz

IPC: H01L21/78 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

公开(公告)号：US10811388B2

公开(公告)日：2020-10-20

申请号：US16212248

申请日：2018-12-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L25/065 ,  H01L21/311 ,  H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L23/64

Abstract: Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

公开(公告)号：US10802285B2

公开(公告)日：2020-10-13

申请号：US16292705

申请日：2019-03-05

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar

IPC: G09G5/00 ,  G02B27/01

Abstract: A virtual reality/augmented reality (VR/AR) headset system (including the capability for one or both of virtual reality and augmented reality) includes a remote optical engine. The remote disposition of the optical engine removes many or all of the components of the VR/AR headset system that add weight, heat, and other characteristics that can add to user discomfort in using the system from the headset. An electronic image is received and/or generated remotely at the optical engine, and is transmitted optically from the remote location to the headset to be viewed by the user. One or more optical waveguides may be used to transmit the electronic image to one or more passive displays of the headset, from the remote optical engine.

公开(公告)号：US10600747B2

公开(公告)日：2020-03-24

申请号：US16217622

申请日：2018-12-12

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Javier A. Delacruz

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/498 ,  H01L25/16 ,  H01L21/48 ,  H01L49/02 ,  H01L23/00

Abstract: Vertical capacitors for microelectronics are provided. An example thin capacitor layer can provide one or numerous capacitors to a semiconductor chip or integrated circuit. In an implementation, a thin capacitor layer of 50-100 μm thickness may have 5000 vertically disposed capacitor plates per linear centimeter, while occupying only a thin slice of the package. Electrodes for each capacitor plate are accessible at multiple surfaces. Electrode density for very fine pitch interconnects can be in the range of 2-200 μm separation between electrodes. A redistribution layer (RDL) may be fabricated on one or both sides of the thin capacitor layer to provide fan-out ball grid arrays that occupy insignificant space. RDLs or through-vias can connect together sets of the interior vertical capacitor plates within a given thin capacitor layer to form various capacitors from the plates to meet the needs of particular chips, dies, integrated circuits, and packages.

公开(公告)号：US10593563B2

公开(公告)日：2020-03-17

申请号：US15873218

申请日：2018-01-17

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L23/498 ,  H01L21/683 ,  H01L23/31

Abstract: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package. Assemblies may be constructed with the semiconductor dies face-up or face-down. One or more redistribution layers (RDLs) may be built on one or both sides of an assembly with resist vias.

公开(公告)号：US10566310B2

公开(公告)日：2020-02-18

申请号：US15095629

申请日：2016-04-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L25/00

Abstract: A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

公开(公告)号：US10475733B2

公开(公告)日：2019-11-12

申请号：US16156595

申请日：2018-10-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/38 ,  H01L21/02 ,  H01L21/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L23/498 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367 ,  H01L23/48 ,  H01L23/36

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.