Invention Grant
- Patent Title: Debug architecture
- Patent Title (中): 调试架构
-
Application No.: US13938077Application Date: 2013-07-09
-
Publication No.: US09176552B2Publication Date: 2015-11-03
- Inventor: Andrew Brian Thomas Hopkins
- Applicant: UltraSoC Technologies Ltd.
- Applicant Address: GB Cambridge
- Assignee: ULTRASOC TECHNOLOGIES LTD.
- Current Assignee: ULTRASOC TECHNOLOGIES LTD.
- Current Assignee Address: GB Cambridge
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Warren S. Wolfeld
- Priority: GB1212179 20120709
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/26 ; G06F11/00 ; G06F9/44 ; G06F1/24 ; G06F1/30 ; G06F11/36 ; G06F11/263 ; G06F11/267 ; G06F15/78

Abstract:
Roughly described, a method of powering down a portion of an integrated circuit chip, the portion of the integrated circuit chip comprising a plurality of peripheral circuits, each peripheral circuit being connected to a respective debug unit, the method comprising: prior to power down, extracting from each debug unit configuration information of that debug unit; storing the configuration information of the debug units in a memory on the integrated circuit chip during power down of the portion of the integrated circuit chip; and on power up, restoring the configuration information of each debug unit to that debug unit prior resuming operation of that debug unit and the peripheral circuit connected to that debug unit.
Public/Granted literature
- US20140013145A1 DEBUG ARCHITECTURE Public/Granted day:2014-01-09
Information query