Invention Grant
- Patent Title: Compliant interconnects in wafers
- Patent Title (中): 晶圆上的兼容互连
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Application No.: US14451136Application Date: 2014-08-04
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Publication No.: US09224649B2Publication Date: 2015-12-29
- Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
- Applicant: Tessera, Inc.
- Applicant Address: US CA San Jose
- Assignee: TESSERA, INC.
- Current Assignee: TESSERA, INC.
- Current Assignee Address: US CA San Jose
- Agency: Haynes and Boone, LLP
- Main IPC: H01L23/488
- IPC: H01L23/488 ; H01L21/60 ; H01L21/768 ; H01L23/48 ; H01L23/00 ; H01L25/065 ; H01L25/00 ; H01L23/31
Abstract:
A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.
Public/Granted literature
- US20140342503A1 COMPLIANT INTERCONNECTS IN WAFERS Public/Granted day:2014-11-20
Information query
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